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19-2227; Rev 2; 3/05
Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers
General Description
The MAX6950/MAX6951 are compact common-cathode display drivers that interface microprocessors to individual 7-segment numeric LED digits, bar graph, or discrete LEDs through an SPITM-, QSPITM-MICROWIRETMcompatible serial interface. The supply voltage can be as low as 2.7V. The MAX6950 drives up to five 7-segment digits or 40 discrete LEDs. The MAX6951 drives up to eight 7-segment digits or 64 discrete LEDs. Included on-chip are hexadecimal character decoders (0-9, A-F), multiplex scan circuitry, segment and digit drivers, and a static RAM that stores each digit. The user may select hexadecimal decoding or no-decode for each digit to allow any mix of 7-segment digits, bar graph, or discrete LEDs to be driven. The segment current for the LEDs is set by an internal digital brightness control. The segment drivers are slew-rate limited to reduce EMI. Individual digits may be addressed and updated without rewriting the entire display. The devices include a low-power shutdown mode, digital brightness control, a scan-limit register that allows the user to display from one to eight digits, segment blinking that can be synchronized across drivers, and a test mode that forces all LEDs on.
Features
High-speed 26MHz SPI-, QSPI-, MICROWIRECompatible Serial Interface +2.7V to +5.5V Operation Individual LED Segment Control Segment Blinking Control that Can Be Synchronized Across Multiple Drivers Hexadecimal Decode/No-Decode Digit Selection Digital Brightness Control Display Blanked on Power-Up Drives Common-Cathode LED Digits Multiplex Clock Syncronizable to External Clock Slew-Rate Limited Segment Drivers for Low EMI 75A Low-Power Shutdown (Data Retained) Small 16-Pin QSOP Package
MAX6950/MAX6951
Ordering Information
PART MAX6950CEE MAX6950EEE MAX6951CEE MAX6951EEE TEMP RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C PIN-PACKAGE 16 QSOP-EP* 16 QSOP-EP* 16 QSOP-EP* 16 QSOP-EP*
Applications
Set-Top Boxes Panel Meters White Goods Bar Graphs and Matrix Displays Industrial Controllers and Instrumentation Professional Audio Equipment Medical Equipment
*EP = Exposed pad.
Pin Configuration
TOP VIEW
DIN 1 CLK 2 16 V+ 15 CS 14 DIG4/SEG4
Functional Diagram appears at end of data sheet. Typical Application appears at end of data sheet.
DIG3/SEG3 3 DIG2/SEG2 4 DIG1/SEG1 5
MAX6950 MAX6951
13 (DIG5)/SEG5 12 (DIG6)/SEG6 11 (DIG7)/SEG7 10 SEG8 9 OSC
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
DIG0/SEG0 6 ISET 7 GND 8
( ) MAX6951 ONLY
QSOP
________________________________________________________________ Maxim Integrated Products
1
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
ABSOLUTE MAXIMUM RATINGS
Voltage (with Respect to GND) V+..................................... ...................................-0.3V to 6V All Other Pins................................................-0.3V to (V+ + 0.3V) DIG1-DIG8 Sink Current.................................................. 440mA SEG1-SEG9 Source Current.............................................. 55mA Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.34mW/C above +70C)........667mW Operating Temperature Ranges (TMIN to TMAX) MAX695_CEE....................................................0C to +70C MAX695_EEE .................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical operating circuit, V+ = +3.0V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER Operating Supply Voltage Shutdown Supply Current SYMBOL V+ ISHDN Shutdown mode, all digital inputs at V+ or GND Overtemperature TA = +25oC CONDITIONS MIN 2.7 75 62 10 1 4 1 155 155 625 1.7 75.5 50 50 8 1250 1250 160 15 8 MHz TYP MAX 5.5 UNITS V A
Operating Supply Current
I+
All segments on, all digits scanned, intensity set to full, internal oscillator, no display load connected OSC = RC oscillator
mA
Master Clock Frequency (OSC Internal Oscillator) Master Clock Frequency (OSC External Clock) Display Scan Rate (OSC External Clock) Display Scan Rate (OSC Internal Oscillator) Display Scan Rate (OSC Internal Oscillator) OSC Internal/External Detection Threshold Dead Clock Protection Frequency OSC High Time (OSC External Clock) OSC Low Time (OSC External Clock)
fOSC
OSC = RC oscillator, RSET = 56k, CSET = 27pF OSC overdriven externally Eight digits scanned, OSC = overdriven externally Eight digits scanned, OSC = RC oscillator Eight digits scanned, OSC = RC oscillator, RSET = 56k, CSET = 27pF
fOSC fSCAN fSCAN fSCAN VOSC fOSC tCH tCL
MHz Hz Hz Hz V kHz ns ns
2
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers
ELECTRICAL CHARACTERISTICS
(Typical operating circuit, V+ = +3.0V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER Slow Segment Blink Period (Internal Oscillator) Fast Segment Blink Period (Internal Oscillator) Fast or Slow Segment Blink Duty Cycle (Note 2) Digit Drive Sink Current Segment Drive Source Current Digit Drive Sink Current (Note 2) Segment Drive Source Current (Note 2) Slew Rate Rise Time LOGIC INPUTS Input Current DIN, CLK, CS Logic High Input Voltage DIN, CLK, CS Logic Low Input Voltage DIN, CLK, CS Hysteresis Voltage DIN, CLK, CS CLK Clock Period CLK Pulse Width High CLK Pulse Width Low CS Fall to CLK Rise Setup Time CLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time CS Pulse High CLK Clock Period CLK Pulse Width High CLK Pulse Width Low CS Fall to CLK Rise Setup Time CLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time CS Pulse High IIH, IIL VIH VIL VI tCP tCH tCL tCSS tCSH tDS tDH tCSW tCP tCH tCL tCSS tCSH tDS tDH tCSW 38.4 19 19 9.5 3 9.5 0 19 50 24 24 12 4 12 4 24 0.5 VIN = 0 or V+ -2 2.4 0.4 2 A V V V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns IDIGIT ISEG IDIGIT ISEG ISEG/t TA = +25C, VLED = 2.4V TA = +25C, VLED = 2.4V TA = +25C, V+ = 2.7V to 3V, VLED = 2.2V TA = +25C, V+ = 2.7V to 3V, VLED = 2.2V TA = +25C SYMBOL fSLOWBLINK fFASTBLINK CONDITIONS Eight digits scanned, OSC = RC oscillator, RSET = 56k, CSET = 27pF Eight digits scanned, OSC = RC oscillator, RSET = 56k, CSET = 27pF 49.9 240 -30 80 -10 35 MIN TYP 1 0.5 50 320 -40 50.1 400 -50 MAX UNITS s s % mA mA mA mA mA/s
MAX6950/MAX6951
TIMING CHARACTERISTICS (Figure 1)
TIMING CHARACTERISTICS (V+ = +2.7V) (Note 2)
Note 1: All parameters tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design.
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
Typical Operating Characteristics
(Typical operating circuit, scan limit set to eight digits, V+ = +3.3V, VLED = 2.4V, TA = +25C, unless otherwise noted.)
INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE
MAX6950/1 toc01
INTERNAL OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
4.30 4.20 4.10 4.00 3.90 3.80 3.70
MAX6950/1 toc02
4.40 4.30 OSCILLATOR FREQUENCY (MHz) 4.20 4.10 V+ = 3.3V 4.00 3.90 3.80 3.70 3.60 -40 -20 40 TEMPERATURE (C) 0 20 60 80 V+ = 5V V+ = 2.7V
4.40 OSCILLATOR FREQUENCY (MHz)
3.60 2 3 4 SUPPLY VOLTAGE (V) 5 6
INTERNAL OSCILLATOR WAVEFORM AT OSC (PIN 9)
MAX6950/1 toc03
DEAD CLOCK OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
79 OSCILLATOR FREQUENCY (kHz) 78 77 76 75 74 73 72 71
MAX6950/1 toc04
80
3.0 2.5 2.0 1.5 1.0 0.5 0 0 200 400 600 800 TIMELINE (ns)
VOLTAGE AT OSC (V)
70 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V)
SEGMENT SOURCE CURRENT vs. SUPPLY VOLTAGE
MAX6950/1 toc05
WAVEFORM AT SEGO/DIGO (PIN 6) V+ = 3.3V, 8 DIGITS SCANNED, 8/16 INTENSITY
MAX6950/1 toc06
1.01 CURRENT NORMALIZED TO 40mA 1.00 0.99 0.98 0.97 0.96 0.95 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
3.5 3.0 2.5 VOLTAGE (V) 2.0 1.5 DIGIT 0 MULTIPLEX TIMESLOT 1.0 0.5 0
6.0
0
500
SUPPLY VOLTAGE (V)
1000 TIMELINE (ns)
1500
2000
4
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers
Pin Description
PIN 1 2 NAME DIN CLK FUNCTION Serial Data Input. Data is loaded into the internal 16-bit Shift register on CLK's rising edge. Serial-Clock Input. On CLK's rising edge, data is shifted into the Internal Shift register. On CLK's falling edge, data is clocked out of DOUT. CLK input is active only while CS is low. Digit X outputs sink current from the display common cathode when acting as digit drivers. Segment X drivers source current to the display. Segment/digit drivers are high impedance when turned off. Current Setting. Connect to GND through a resistor (RSET) to set the peak current. This resistor, together with capacitor CSET, also sets the multiplex clock frequency. Ground Multiplexer Clock Input. A capacitor (CSET) is connected to GND when the internal RC oscillator multiplex clock is used. Resistor RSET (also used to set the peak current) and capacitor CSET together set the multiplex clock frequency. When the external clock is used, OSC should be driven by a 1MHz to 8MHz clock. Chip-Select Input. Serial data is loaded into the Shift register while CS is low. The last 16 bits of serial data are latched on CS's rising edge. Positive Supply Voltage. Bypass to GND with a 0.1F capacitor. Exposed pad on package underside. Connect to GND.
MAX6950/MAX6951
3-6, 10-14
DIGX, SEGX
7 8
ISET GND
9
OSC
15 16 PAD
CS V+ Exposed pad
Detailed Description
Differences Between MAX6950 and MAX6951
The MAX6950 is a five-digit common-cathode display driver. It drives five digits, with each digit comprising eight LEDs with cathodes connected to a common cathode. The display limit is therefore 40 LEDs or digit segments. The MAX6951 is an eight-digit common-cathode display driver. It drives eight digits, with each digit comprising eight LEDs. The only difference between the MAX6950 and MAX6951 is that the MAX6950 is missing three digit drivers. The MAX6950 can be configured to scan eight digits, but if the last three digits are wired up, they do not light. The MAX6950/MAX6951 use a unique multiplexing scheme to minimize the connections between the driver and LED display. The scheme requires that the segment connections are different to each of the five (MAX6950) or eight (MAX6951) digits (Table 1). This is shown in the Typical Application Circuit, which uses single-digit type displays. The MAX6950/MAX6951 are not intended to drive multidigit display types, which have the segments internally wired together, unless the
segments are wired with the common cathodes to follow Table 1. The MAX6950/MAX6951 can drive multidigit LED displays that have the segments individually pinned for each digit because then the digits can be connected together correctly externally, just as if individual digits were used.
Serial-Addressing Modes
The microprocessor interface on the MAX6950/ MAX6951 is a SPI-compatible 3-wire serial interface using three input pins (Figure 1). This interface is used to write configuration and display data to the MAX6950/ MAX6951. The serial interface data word length is 16 bits, which are labeled D15-D0 (Table 2). D15-D8 contain the command address, and D7-D0 contain the data. The first bit received is D15, the most-significant bit (MSB). The three input pins are: * * CLK is the serial clock input, and may idle low or high at the start and end of a write sequence. CS is the MAX6950/MAX6951s' chip-select input, and must be low to clock data into the MAX6950/ MAX6951. DIN is the serial data input, and must be stable when it is sampled on the rising edge of the clock.
*
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
Table 1. Standard Driver Connection to Single-Digit Displays
DIG/SEG0 PIN 6 LED Digit 0 LED Digit 1 LED Digit 2 LED Digit 3 LED Digit 4 LED Digit 5 LED Digit 6 LED Digit 7 CC0 SEG dp SEG dp SEG dp SEG dp SEG dp SEG dp SEG dp DIG/SEG1 PIN 5 SEG dp CC1 SEG g SEG g SEG g SEG g SEG g SEG g DIG/SEG2 PIN 4 SEG g SEG g CC2 SEG f SEG f SEG f SEG f SEG f DIG/SEG3 PIN 3 SEG f SEG f SEG f CC3 SEG e SEG e SEG e SEG e DIG/SEG4 PIN 14 SEG e SEG e SEG e SEG e CC4 SEG d SEG d SEG d DIG/SEG5 PIN 13 SEG d SEG d SEG d SEG d SEG d CC5 SEG c SEG c DIG/SEG6 PIN 12 SEG c SEG c SEG c SEG c SEG c SEG c CC6 SEG b DIG/SEG7 PIN 11 SEG b SEG b SEG b SEG b SEG b SEG b SEG b CC7 SEG 8 PIN 10 SEG a SEG a SEG a SEG a SEG a SEG a SEG a SEG a
Table 2. Serial-Data Format (16 Bits)
D15 D14 D13 D12 D11 D10 D9 D8 D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB ADDRESS DATA
The serial interface comprises a 16-bit shift register into which DIN data is clocked on the rising edge of CLK when CS is low. When CS is high, transitions on CLK do not clock data into the shift register. When CS goes high, the 16 bits in the shift register are parallel loaded into a 16-bit latch. The 16 bits in the latch are then decoded to determine and execute the command. The MAX6950/MAX6951 are written to using the following sequence (Figure 2): 1) Take CLK low. 2) Take CS low. This enables the internal 16-bit shift register. 3) Clock 16 bits of data in order, D15 first to D0 last, into DIN, observing the setup and hold times. 4) Take CS high. CLK and DIN may well be used to transmit data to other peripherals. The MAX6950/MAX6951 ignore all activity on CLK and DIN except when CS is low. Data cannot be read from the MAX6950/MAX6951. If fewer or greater than 16 bits are clocked into the MAX6950/MAX6951 between taking CS low and taking CS high again, the MAX6950/MAX6951 store the last 16 bits received, including the previous transmission(s). The general case is when n bits (where n > 16) are transmitted to the MAX6950/MAX6951. The last bits comprising bits {n-15} to {n} are retained and are parallel loaded into the 16-bit latch as bits D15 to D0, respectively (Figure 3).
Digit and Control Registers
Table 3 lists the addressable Digit and Configuration registers. The digit registers are implemented by two planes of 8-byte dual-port SRAM, P0 and P1.
Initial Power-Up
On initial power-up, all control registers are reset, the display is blanked, and the MAX6950/MAX6951 enter shutdown mode. Program the display driver prior to display use. Otherwise, it is initially set to scan five digits, it does not decode data in the data registers, and the Intensity register is set to its minimum value. Table 4 lists the register status after power-up.
Configuration Register
The configuration register is used to enter and exit shutdown, select the blink rate, globally enable and disable the blink function, globally clear the digit data, and reset the blink timing. Bit position D1 should always be written with a zero when the configuration register is updated. See Table 5 for configuration register format. The S bit selects shutdown or normal operation. The B bit selects the blink rate. The E bit globally enables or disables the blink function. The T bit resets the blink timing. The R bit globally clears the digit data for both planes P0 and P1 for all digits. When the MAX6950/MAX6951 are in shutdown mode (Table 6), the scan oscillator is halted; all segment and digit drivers are high impedance. Data in the digit and
6
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
CS tCSW
tCSS
tCL
tCH
tCP
tCSH
CLK tDS DIN
tDH D14 D1 D0
D15
Figure 1. Timing Diagram
CS
CLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 2. Transmission of 16 Bits to the MAX6950/MAX6951
CS
CLK DIN BIT1 BIT2 N-15 N-14 N-13 N-12 N-11 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N
Figure 3 . Transmission of More than 16 Bits to the MAX6950/MAX6951
control registers remains unaltered. Shutdown can be used to save power. For minimum supply current in shutdown mode, logic inputs should be at ground or V+ (CMOS-logic levels). The display driver can be programmed while in shutdown mode, and shutdown mode can be overridden by the display test function. Table 7 lists the blink rate selection format. If blink is globally enabled by setting the E bit of the configuration register (Table 8), then the digit data in both planes P0 and P1 are used to control the display (Table 9).
When the global blink timing synchronization bit is set, the multiplex and blink timing counter is cleared on the rising edge of CS. By setting the T bit in multiple MAX6950/MAX6951s at the same time (or in quick succession), the blink timing can be synchronized across all the devices. When the global digit data clear (R data bit D5) is set, the digit data for both planes P0 and P1 for ALL digits is cleared on the rising edge of CS. Digits with decode enabled display the zero. Digits without decode enabled show all segments unlit.
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
Table 3. Register Address Map
REGISTER No-Op Decode Mode Intensity Scan Limit Configuration Factory reserved. Do not write to this. Display Test Digit 0 plane P0 only (plane 1 unchanged) Digit 1 plane P0 only (plane 1 unchanged) Digit 2 plane P0 only (plane 1 unchanged) Digit 3 plane P0 only (plane 1 unchanged) Digit 4 plane P0 only (plane 1 unchanged) Digit 5 plane P0 only (plane 1 unchanged) Digit 6 plane P0 only (plane 1 unchanged) Digit 7 plane P0 only (plane 1 unchanged) Digit 0 plane P1 only (plane 0 unchanged) Digit 1 plane P1 only (plane 0 unchanged) Digit 2 plane P1 only (plane 0 unchanged) Digit 3 plane P1 only (plane 0 unchanged) Digit 4 plane P1 only (plane 0 unchanged) Digit 5 plane P1 only (plane 0 unchanged) Digit 6 plane P1 only (plane 0 unchanged) Digit 7 plane P1 only (plane 0 unchanged) Digit 0 plane P0 and plane P1 (with same data) Digit 1 plane P0 and plane P1 (with same data) Digit 2 plane P0 and plane P1 (with same data) Digit 3 plane P0 and plane P1 (with same data) Digit 4 plane P0 and plane P1 (with same data) Digit 5 plane P0 and plane P1 (with same data) Digit 6 plane P0 and plane P1 (with same data) Digit 7 plane P0 and plane P1 (with same data) COMMAND ADDRESS D15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D13 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D10 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D9 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX CODE 0x00 0x01 0x02 0x03 0x04 0x06 0x07 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67
No-Op Register
The no-op register is used when the MAX6950/ MAX6951 are connected as the last device on a chain of cascaded SPI devices. To write the other cascaded device(s), ensure that while the intended device receives its specific command, the MAX6950/MAX6951 receive a no-op command.
Display-Test Register
The display-test register switches the drivers between one of two modes: normal and display test. Display-test mode turns all LEDs on by overriding, but not altering, all control and digit registers (including the Shutdown register) In display-test mode, eight digits are scanned and the duty cycle is 7/16 (half power). Table 11 lists the display-test register format.
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
Table 4. Initial Power-Up Register Status
REGISTER Decode Intensity Scan Limit Configuration Display Test Digit 0 Digit 1 Digit 2 Digit 3 Digit 4 Digit 5 Digit 6 Digit 7 POWER-UP CONDITION No decode for digits 7-0 1/16 (min on) Display 5 digits: 0 1 2 3 4 Shutdown enabled/blink speed is slow/blink disabled Normal operation Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes ADDRESS CODE (HEX) 0x01 0x02 0x03 0x04 0x07 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 REGISTER DATA D7 0 X X X X 0 0 0 0 0 0 0 0 D6 0 X X X X 0 0 0 0 0 0 0 0 D5 0 X X X X 0 0 0 0 0 0 0 0 D4 0 X X 0 X 0 0 0 0 0 0 0 0 D3 0 0 X 0 X 0 0 0 0 0 0 0 0 D2 0 0 1 0 X 0 0 0 0 0 0 0 0 D1 0 0 0 0 X 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0
Scan-Limit Register
The scan-limit register sets how many digits are displayed, from one to eight digits. It is possible to set the MAX6950 (the five-digit part) to scan six, seven, or eight digits. The MAX6951 set to eight digits displays five digits less brightly than if it had been set to scan five digits, but the brightness would match that of a MAX6951 used in the same system if the Intensity registers are set to the same value. For example, consider an 11-digit requirement. This can be served by using a MAX6950 to drive five digits plus a MAX6951 to drive six digits. Both parts are configured to drive six digits to ensure the brightness is the same. The digits are displayed in a multiplexed manner with a typical display scan rate of 1kHz with five digits displayed or 625Hz with eight digits displayed with fOSC = 4MHz. Since the number of scanned digits affects the display brightness, the Scan-Limit register should not be used to blank portions of the display (such as for leading-zero suppression). Table 12 lists the scan-limit register format.
Decode Mode Register
The decode mode register sets hexadecimal code (0-9, A-F) or no-decode operation for each digit. Each bit in the register corresponds to one digit. A logic high selects hexadecimal code font decoding for that digit, while logic low bypasses the decoder. Digits may be set for decode or no-decode in any combination. Examples of the decode mode control register format are shown in Table 14. When the hexadecimal code-decode mode is used, the decoder looks only at the lower nibble of the data in the digit register (D3-D0), disregarding bits D6-D4. D7, which sets the decimal point (SEG DP), is independent of the decoder, and is positive logic (D7 = 1 turns the decimal point on). Table 15 lists the hexadecimal code font. When no-decode is selected, data bits D7-D0 correspond to the segment lines of the MAX6950/ MAX6951. Table 15 shows the one-to-one pairing of each data bit to the appropriate segment line.
Display Digit Registers
The MAX6950/MAX6951 use a digit register to store the data that the user wishes to display on the LED digits. These digit registers are implemented by two planes of 8-byte, dual-port SRAM, called P0 and P1. The digit registers are dual port to enable them to be written to through the SPI interface, asynchronous to being read to multiplex the display.
Intensity Register
Digital control of display brightness is provided by an internal pulse-width modulator, which is controlled by the lower nibble of the intensity register (Figure 4). The modulator scales the average segment current in 16 steps from a minimum of 15/16 down to 1/16 of the peak current. The minimum interdigit blanking time is set to 1/16 of a cycle. See Table 13 for Intensity register format.
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
Table 5. Configuration Register Format
MODE Configuration register ADDRESS CODE (HEX) 0x04 REGISTER DATA D7 X D6 X D5 R D4 T D3 E D2 B D1 0 D0 S
Table 6. Shutdown Control (S Data Bit D0) Format
MODE Shutdown Normal operation ADDRESS CODE (HEX) 0x04 0x04 REGISTER DATA D7 X X D6 X X D5 R R D4 T T D3 E E D2 B B D1 0 0 D0 0 1
Table 7. Blink Rate Selection (B Data Bit D2) Format
MODE Slow-blinking segments blink on for 1s, off for 1s with fOSC = 4MHz Fast-blinking segments blink on for 0.5s, off for 0.5s with fOSC = 4MHz ADDRESS CODE (HEX) REGISTER DATA D7 X D6 X D5 R D4 T D3 E D2 0 D1 0 D0 S
0x04
0x04
X
X
R
T
E
1
0
S
Table 8. Global Blink Enable/Disable (E Data Bit D3) Format
MODE Blink function is disabled Blink function is enabled ADDRESS CODE (HEX) 0x04 0x04 REGISTER DATA D7 X X D6 X X D5 R R D4 T T D3 0 1 D2 B B D1 0 0 D0 S S
Table 9. Global Blink Timing Synchronization (T Data Bit D4) Format
MODE Blink timing counters are unaffected Blink timing counters are cleared on the rising edge of CS ADDRESS CODE (HEX) 0x04 REGISTER DATA D7 X D6 X D5 R D4 0 D3 E D2 B D1 0 D0 S
0x04
X
X
R
1
E
B
0
S
Each LED digit is represented by 2 bytes of memory, 1 byte in plane P0 and the other in plane P1. Each LED digit's segment is represented by 2 bits of memory, 1 bit from the appropriate byte in each plane. The digit
10
registers are mapped so that a digit's data can be updated in plane P0, or plane P1, or both planes at the same time (Table 3).
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
Table 10. Global Clear Digit Data (R Data Bit D5) Format
MODE Digit data for both planes P0 and P1 are unaffected Digit data for both planes P0 and P1 are cleared on the rising edge of CS ADDRESS CODE (HEX) 0x04 REGISTER DATA D7 X D6 X D5 0 D4 T D3 E D2 B D1 0 D0 S
0x04
X
X
1
T
E
B
0
S
Table 11. Display-Test Register Format
MODE Normal operation Display test ADDRESS CODE (HEX) 0x07 0x07 REGISTER DATA D7 X X D6 X X D5 X X D4 X X D3 X X D2 X X D1 X X D0 0 1
Table 12. Scan-Limit Register Format
SCAN LIMIT Display digit 0 only Display digits 0 and 1 Display digits 0 and 1 2 Display digits 0 and 1 2 3 Display digits 0 and 1 2 3 4 Display digits 0 and 1 2 3 4 5 Display digits 0 and 1 2 3 4 5 6 Display digits 0 and 1 2 3 4 5 6 7 ADDRESS CODE (HEX) 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 REGISTER DATA D7 X X X X X X X X D6 X X X X X X X X D5 X X X X X X X X D4 X X X X X X X X D3 X X X X X X X X D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 HEX CODE 0xX0 0xX1 0xX2 0xX3 0xX4 0xX5 0xX6 0xX7
If the blink function is disabled through the Blink Enable Bit E (Table 8) in the configuration register, then the digit register data in plane P0 is used to multiplex the display. The digit register data in P1 is not used (Table 17). If the blink function is enabled, then the digit register data in both plane P0 and plane P1 are alternately used to multiplex the display. Blinking is achieved by multiplexing the LED display using data plane P0 and plane P1 on alternate phases of the blink clock (Table 18).
on and off. Once blinking has been configured, it continues automatically without further intervention.
Blink Speed
The blink speed is determined by frequency of the multiplex clock, OSC, and by the setting of the Blink Rate Selection Bit B (Table 7) in the configuration register. The Blink Rate Selection Bit B sets either fast or slow blink speed for the whole display.
Display Blink Mode
The display blinking facility, when enabled, makes the driver flip automatically between displaying the digit register data in planes P0 and plane P1. If the digit register data for any individual segment is different in the two planes, then that segment appears to blink or flash
Multiplex Clock and OSC Oscillator
The OSC input pin is used to set both the display scan rate and the blink timing for the display driver. OSC must either be fitted with an external capacitor CSET to GND to set the frequency of the MAX6950/MAX6951s' internal RC oscillator, or be overdriven with an external TTL/CMOS clock.
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
Table 13. Intensity Register Format
DUTY CYCLE 1/16 (min on) 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 15/16 (max on) TYPICAL SEGMENT CURRENT (mA) 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 37.5 37.5 ADDRESS CODE (HEX) 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 X X X X X X X X X X X X X X X X D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX CODE 0xX0 0xX1 0xX2 0xX3 0xX4 0xX5 0xX6 0xX7 0xX8 0xX9 0xXA 0xXB 0xXC 0xXD 0xXE 0xXF
The allowed range of the frequency at the OSC pin, fOSC, is 1MHz to 8MHz, which allows the blink frequency to be adjusted over a wide range. The internal oscillator may be accurate enough for many applications using a single device. If an exact or synchronized blink rate is required, then OSC should be driven by an external clock. The display scan rate (defined in the Electrical Characteristics table) is calculated by dividing fOSC by 4000 for the MAX6950 (scanning a full five digits), or by 6400 for the MAX6951 (scanning a full eight digits). The display scan rate is the refresh rate for all the digits of the display. With fOSC at 4MHz, each display digit is enabled for 200s. There is a fail-safe circuit in the MAX6950/MAX6951 to ensure the display multiplexing works if the OSC is configured incorrectly. This ensures that the driver cannot remain stuck on a single digit, forcing a peak current continuously through segments. The fail-safe circuit detects that fOSC is too slow, and generates extra clock transitions to guarantee a minimum effective clock of typically 75.5kHz. The scan rate for eight digits is about 11Hz in fail-safe mode, and appears to flicker to most observers. A flickering display is a good indication that there is a problem with the multiplex clock. The clock failure detection works regardless of the clock source being the internal RC oscillator or external clock drive.
The RC oscillator uses an external resistor RSET (which also sets the peak segment current) and an external capacitor CSET to set the oscillator frequency. The recommended values of RSET and CSET set the oscillator at 4MHz, which makes the slow and fast blink frequency 0.5Hz and 1Hz, respectively.
Synchronization of Blinking Across Multiple MAX6950/MAX6951 Drivers
The OSC inputs of multiple MAX6950/MAX6951 drivers can be connected together to an external clock to make the devices blink at the same frequency. Segment blinking may be synchronized across multiple MAX6950/ MAX6951s so that all drivers blink not only at the same frequency, but also in phase. When the control register is written with the T bit set (Table 9), the OSC divider chain is cleared and the display multiplexing sequence reset. To synchronize several drivers, it is necessary to write this register in all drivers at the same time. In practice, adequate synchronization can be achieved by writing to multiple drivers in quick succession. When the global blink timing synchronization bit is set, the multiplexing and blink counter is cleared on the rising edge of CS. By setting the T bit in multiple MAX6950/MAX6951s at the same time (or in quick succession), the blink timing can be synchronized across all the devices. Note that the display multiplexing
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
ONE COMPLETE 1.6ms MULTIPLEX CYCLE AROUND 8 DIGITS START OF NEXT CYCLE 200s TIME SLOT DIGIT 0 200s TIME SLOT DIGIT 1 200s TIME SLOT DIGIT 2 200s TIME SLOT DIGIT 3 200s TIME SLOT DIGIT 4 200s TIME SLOT DIGIT 5 200s TIME SLOT DIGIT 6 200s TIME SLOT DIGIT 7 200s TIME SLOT DIGIT 0
DIGIT CATHODE DRIVER INTENSITY SETTINGS HIGH-Z 1/16TH (MIN ON) LOW CURRENT SOURCE ENABLED ANODE MIN ON HIGH-Z HIGH-Z HIGH-Z 2/16TH LOW 3/16TH LOW
DIGIT 0's 200s MULTIPLEX TIME SLOT
HIGH-Z
HIGH-Z 13/16TH LOW HIGH-Z 14/16TH LOW HIGH-Z 15/16TH LOW HIGH-Z 16/16TH MAX ON LOW
MINIMUM 12.5s INTERDIGIT BLANKING INTERVAL CURRENT SOURCE ENABLED ANODE MAX ON HIGH-Z ANODE (UNLIT) HIGH-Z HIGH-Z HIGH-Z
Figure 4. Multiplex and Intensity Timing Diagram
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
Table 14. Decode-Mode Register Examples
DECODE CODE No decode for digits 7-0 Hexadecimal decode for digit 0, no decode for digits 7-1 Hexadecimal decode for digits 2-0, no decode for digits 7-3 Hexadecimal decode for digits 7-0 ADDRESS CODE (HEX) 0x01 0x01 0x01 0x01 REGISTER DATA D7 0 0 0 1 D6 0 0 0 1 D5 0 0 0 1 D4 0 0 0 1 D3 0 0 0 1 D2 0 0 1 1 D1 0 0 1 1 D0 0 1 1 1 HEX CODE 0x00 0x01 0x07 0xFF
Table 15. Hexadecimal Font
7-SEGMENT CHARACTER 0 1 2 3 4 5 6 7 8 9 A B C D E F REGISTER DATA D7* D6-D4 X X X X X X X X X X X X X X X X D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 dp* a 1 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 b 1 1 1 1 1 0 0 1 1 1 1 0 0 1 0 0 ON SEGMENTS = 1 c 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 d 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 e 1 0 1 0 0 0 1 0 1 0 1 1 1 1 1 1 f 1 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 g 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1
The decimal point segment is lit when bit D7 = 1.
sequence is also reset, which might give rise to a onetime display flicker when the register is written.
Selecting External Components RSET and CSET to Set Oscillator Frequency and Segment Current
The RC oscillator uses an external resistor RSET and an external capacitor CSET to set the oscillator frequency, fOSC. The allowed range of fOSC is 1MHz to 8MHz. RSET also sets the peak segment current. The recommended values of RSET and CSET set the oscillator to
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4MHz, which makes the blink frequencies 0.5Hz and 1Hz. The recommended value of RSET also sets the peak current to 40mA, which makes the segment current adjustable from 2.5mA to 37.5mA in 2.5mA steps. ISEG = KI / RSET mA fOSC = KF / (RSET CSET + CSTRAY) MHz Where: KI = 2240
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers
Table 16. No-Decode Mode Data Bits and Corresponding Segment Lines
REGISTER DATA D7 Segment line dp D6 a D5 b D4 c D3 d D2 e D1 f D0 g
LEDs chosen are rated to withstand a reverse bias equal to the maximum supply voltage applied to the MAX6950/MAX6951.
MAX6950/MAX6951
Applications Information
Choosing Supply Voltage to Minimize Power Dissipation
The MAX6950/MAX6951 drive a peak current of 40mA into LEDs with a 2.4V forward-voltage drop when operated from a supply voltage of at least 3.0V. The minimum voltage drop across the internal LED drivers is therefore (3.0V - 2.4V) = 0.6V. If a higher supply voltage is used, the driver absorbs a higher voltage, and the driver's power dissipation increases accordingly. However, if the LEDs used have a higher forward voltage drop than 2.4V, the supply voltage must be raised accordingly to ensure that the driver always has at least 0.6V headroom. The voltage drop across the drivers with a nominal +5V supply (5.0V - 2.4V) = 2.6V is nearly 3 times the drop across the drivers with a nominal 3.3V supply (3.3V 2.4V) = 0.9V. In many systems, consumption is an important design criterion, and the MAX6950/MAX6951 should be operated from the system's 3.3V nominal supply. In other designs, the lowest supply voltage may be 5V. The issue now is to ensure the dissipation limit for the MAX6950/MAX6951 is not exceeded. This can be achieved by inserting a series resistor in the supply to the MAX6950/MAX6951, ensuring that the supply decoupling capacitors are still on the MAX6950/ MAX6951 side of the resistor. For example, consider the requirement that the minimum supply voltage to a MAX6951 must be 3.0V, and the input supply range is 5V 5%. Maximum supply current is 15mA + (40mA 8) = 335mA. Minimum input supply voltage is 4.75V. Maximum series resistor value is (4.75V - 3.0V)/0.335A = 5.2. We choose 4.7 10%. Worst-case resistor dissipation is at maximum toleranced resistance, i.e., (0.335A)2 (4.7 1.1) = 0.584W. We choose a 1W resistor rating. The maximum MAX6951 supply voltage is at maximum input supply voltage and minimum toleranced resistance, i.e., 5.25V - (0.335A 4.7 0.9) = 3.83V.
a f g e d c d b
KF = 6720 RSET = external resistor in k CSET = external capacitor in pF CSTRAY = stray capacitance from OSC pin to GND in pF, typically 3pF The recommended value of RSET is 56k and the recommended value of CSET is 27pF. The recommended value of R SET is the minimum allowed value, since it sets the display driver to the maximum allowed segment current. RSET can be set to a higher value to set the segment current to a lower peak value where desired. The user must also ensure that the peak current specifications of the LEDs connected to the driver are not exceeded. The effective value of CSET includes not only the actual external capacitor used, but also the stray capacitance from the OSC pin to GND. This capacitance is usually in the 1pF to 5pF range, depending on the layout used.
Low-Voltage Operation
The MAX6950/MAX6951 work over the +2.7V to +5.5V supply range. The minimum useful supply voltage is determined by the forward voltage drop of the LEDs at the peak current ISEG, plus the 0.6V headroom required by the driver output stages. The MAX6950/MAX6951 correctly regulate ISEG with a supply above this minimum voltage. If the supply drops below this minimum voltage, the driver output stages may brown out, and
15
LED Maximum Reverse Voltage
The display connection scheme used by the MAX6950/MAX6951 puts LED segments in reverse bias during a portion of the multiplexing time. The maximum applied reverse bias voltage is the value of the supply voltage, V+. It is therefore important to ensure that the
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
Table 17. Digit Register Mapping with Blink Globally Disabled
SEGMENT'S BIT SETTING IN PLANE P1 X SEGMENT'S BIT SETTING IN PLANE P0 0 SEGMENT BEHAVIOR Segment off during both halves of each blink period Segment off during both halves of each blink period
V+ = supply voltage DUTY = duty cycle set by intensity register N = number of segment driven (worst case is 8) VLED = LED forward voltage ISEG = segment current set by RSET PD = power dissipation, in mW if currents are in mA Dissipation example: ISEG = 40mA, N = 8, Duty = 15/16, VLED = 2.4V at 40mA, V+ = 3.6V PD = 3.6V (15mA) + (3.6V - 2.4V)(15 / 16 40mA x 8) = 0.414W
X
1
Table 18. Digit Register Mapping with Blink Globally Enabled
SEGMENT'S BIT SETTING IN PLANE P1 0 0 SEGMENT'S BIT SETTING IN PLANE P0 0 1 SEGMENT BEHAVIOR Segment off Segment on only during the 1st half of each blink period Segment on only during the 2nd half of each blink period Segment on
Thus, for the 16-pin QSOP package (TJA = 1/0.00834 = +120C/W), the maximum allowed ambient temperature TA is given by: TJ (MAX) = TA + (PD TJA) = +150C = TA + (0.44 +120C/W) So TA = +100C. Thus, the device can be operated safely at a maximum package temperature of +85C.
Power Supplies
The MAX6950/MAX6951 operate from a single +2.7V to +5.5V power supply. Bypass the power supply to ground with a 0.1F capacitor as close to the pin as possible. Add a 22F capacitor if the MAX6950/ MAX6951 are not close to the board's input bulk decoupling capacitor. Connect the underside exposed pad to GND.
1 1
0 1
be unable to regulate the current correctly. As the supply voltage drops further, the LED segment drive current becomes effectively limited by the output drivers' on-resistance, and the LED drive current drops. The characteristics of each individual LED in a modern 7segment digit usually match well, so the result is that the display intensity dims uniformly as supply voltage drops out of regulation and beyond. The MAX6950/ MAX6951 operate down to 2V supply voltage (although most displays are very dim at this voltage), providing that the MAX6950/MAX6951 are powered up initially to at least 2.7V to trigger the device's internal reset, and also that the SPI interface is constrained to 5Mbps.
Board Layout
When designing a board, use the following guidelines: 1. The RSET connection to pin 7 is a high-impedance node, and sensitive to layout. Place RSET right next to pins 7 and 8 and route RSET directly to these pins with very short tracks. 2. Ensure that the track from the ground end of RSET routes directly to pin 8, and that this track is not used as part of any other ground connection. Figure 5 shows a good layout. The decoupling capacitors C1 (ceramic) and C2 (bulk, if required) are located above the IC. The ground track to RSET is a separate track from both the IC's power ground connection and the ground plane.
Computing Power Dissipation
The upper limit for power dissipation (PD) for the MAX6950/MAX6951 is determined from the following equation: PD = (V+ x I+) + (V+ - VLED) (DUTY ISEG N) Where:
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers
Typical Application Circuit
MAX6950/MAX6951
3.3V C2 22F C1 100nF
16 DIG1-DIG8 SEG1-SEG9
9 8 DIGITS AND SEGMENTS (SEE TABLE 1 FOR CONNECTIONS)
MAX6951
C ISET DIN CS CLK 1 15 2 DIN CS CLK 8 OSC 9 CSET 27pF RSET 56k 7
Chip Information
TRANSISTOR COUNT: 17,350 PROCESS: CMOS
Figure 5. Sample Board Layout
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers MAX6950/MAX6951
Functional Diagram
8 CATHODE DRIVERS 9 ANODE DRIVERS DIG0/SEG0 SEGMENT CURRENT REFERENCE HEXADECIMAL ROM OUT IN MODE 8 PWM BRIGHTNESS CONTROL DIG1/SEG1 DIG2/SEG2 DIG3/SEG3 DIG4/SEG4
ISET
PWM
OSC
MULTIPLEX, PWM BLINK COUNTERS
DIGIT MULTIPLEXER 3 BLINK ENABLE REGISTER BLINK RATE REGISTER BLINK SYNC REGISTER INTENSITY REGISTER DECODE-MODE REGISTER GLOBAL CLEAR REGISTER SCAN-LIMIT REGISTER
(DIG5)/SEG5 (DIG6)/SEG6 (DIG7)/SEG7 DIGIT SEG8 SHUTDOWN TEST
BLINK ENABLE BLINK CONTROL BLINK RATE BLINK SYNC P0 ENABLE P1 ENABLE
3 ENABLE ADDRESS
8 DATA CLR
3 ENABLE ADDRESS
8 DATA CLR
SHUTDOWN REGISTER TEST REGISTER CONFIGURATION REGISTER DATA 8 ENABLE
8-BYTE DUAL-PORT RAM PLANE P0 DATA ADDRESS ENABLE 8 3
8-BYTE DUAL-PORT RAM PLANE P1 DATA ADDRESS ENABLE 8 3
DIGIT AND CONTROL REGISTER ADDRESS DECODER 8 REGISTER ADDRESS REGISTER DATA 0 CS D0 D1 D2 D3 D4 D5 D6 D7 DIGIT/CONTROL ADDRESS D8 D9 D10 0 D11 0 D12 D13 DIGIT PLANE D14 0 D15
DIN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CLK
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Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers
Package Information
QSOP.EPS
MAX6950/MAX6951
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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